DV Dharanika V
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Dharanika V.

I design RTL, FPGA systems and digital hardware that moves from logic to impact.

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I work on FPGA systems, RTL design, verification, and applied AI-driven hardware projects. I build digital systems that are precise, testable, and grounded in real-world engineering.

RTL Design Verilog FPGA VLSI AI & ML
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ACCESS PASS ENG • ECE
Dharanika V portrait

Dharanika V

Coimbatore, India

ROLE

ECE Engineer • RTL, FPGA, VLSI

STACK
C Python Verilog Vivado MATLAB
FOCUS

RTL design, FPGA validation, VLSI, embedded systems

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About

Focused on hardware design, verification, and practical engineering.

I am Dharanika V, an Electronics and Communication Engineering student at PSG Institute of Technology and Applied Research, Coimbatore. My interests are rooted in digital design, FPGA systems, computer architecture, and hardware verification.

Skills

Technical capability across hardware and intelligent systems.

Programming

C Python 8051 Assembly

HDL & Digital Design

Verilog HDL RTL Design FSM Sequential Circuits

Simulation & Tools

Xilinx Vivado Cadence Virtuoso MATLAB Waveform Debugging

Hardware

FPGA SPI AXI DAC Interfaces Embedded Systems

AI & ML

NumPy Pandas Scikit-learn PyTorch Computer Vision

Core Concepts

Digital Electronics Computer Architecture Functional Verification Hardware Debugging

Projects

Work across FPGA, verification, ML, and embedded systems.

Vision AI 2025

Wafer Defect Classification

Developed a Vision Transformer for 9-class semiconductor wafer defect classification, achieving 98.86% test accuracy and 0.9886 macro-F1.

FPGA 2025

Dual-DAC Controller

Designed a Verilog-based dual-DAC controller for Artix-7 FPGA systems with serial update and synchronization logic.

Verification 2024

Synchronous FIFO

Implemented and validated FIFO read/write logic and boundary conditions such as overflow, underflow, and wrap-around.

Embedded 2024

Autonomous Fire Detection Robot

Built an ESP32-driven fire detection robot with flame sensing, motor control, and Blynk-based notifications.

Education

Academic and internship experience rooted in hardware systems.

2023 – 2027

B.E. ECE

PSG Institute of Technology and Applied Research

CGPA: 8.58 / 10
2022 – 2023

HSC

Venkateswara Vidhyalaya Matric Hr. Sec. School

Grade: 97%

Contact

Let’s build something meaningful.

dharanikavaratharaj@gmail.com +91 9566744667 LinkedIn